A field programmable gate array (FPGA) is a versatile integrated circuit, the internal circuitry of which may be configured by an individual user to realize a user-specific circuit. To configure an FPGA, the user configures an on-chip interconnect structure of the FPGA so that selected inputs and selected outputs of selected on-chip logic elements are connected together in such a way that the resulting circuit is the user-specific circuit desired by the user.
FIG. 1 (Prior Art) is a simplified diagram illustrating an integrated circuit 1, including a plurality of interface cells 2-7, two logic modules 8-9, and four routing channels. A first routing channel extends horizontally adjacent to the top side of integrated circuit 1, a second routing channel extends horizontally adjacent to the bottom side of integrated adjacent to the left side of integrated circuit 1 and intersects with the first and second routing channels, and a fourth routing channel extends vertically adjacent to the right side of integrated circuit 1 and intersects with the first and second routing channels. The logic modules 8 and 9 can be coupled together as desired and coupled to the interface cells 2-7 as desired via interconnect in the routing channels.
It is seen that a portion (a "macrocell") of the routing channel and logic module structure of FIG. 1 is repeated. Macrocell 10 is one such portion and macrocell 11 is another such portion. Macrocell 10, for example, contains the third routing channel, the left-most portion of the first and second routing channels, and a plurality of "antifuses" for connecting selected routing conductors together within the macrocell.
Interface cells 2-7 function to receive incoming data into integrated circuit 1 or to transmit outgoing data from integrated circuit 1. It may be desired that data received into integrated circuit 1 is captured in a register ("registered") first before being processed by other circuitry in the logic modules of the integrated circuit. Alternatively, it may be desired that the data is not registered but rather only goes through combinatorial logic on its way to the logic modules. Because interface cells 2-7 do not include registers, one conventional way to register incoming data is to use registers in logic modules to capture the data. Such use of logic module registers as input registers can, however, cause timing problems due to long propagation delays through the integrated circuit and to the registers inside the logic modules.
Another drawback of using logic module registers as input registers is that the logic modules used for this purpose may not be fully utilized and result in inefficient logic use. It may not be possible to use the other logic elements of a logic module for another purpose once the register is used as an input register. Thus, an entire logic module may be consumed for the purpose of serving as an input register. In situations where multiple bits of data from a bus are to be registered, a large number of logic modules may have to be dedicated to the task of registering the incoming data. This may drastically reduce the number of logic modules available for implementing additional logic.
Each of the small square symbols in FIG. 1 represents a connection element referred to as a "cross antifuse". Cross antifuse 12, for example, can be programmed to form a low impedance connection between horizontally extending routing conductor 13 in the second routing channel and vertically extending routing conductor 14 in the fourth routing channel. Each of the small "X" shaped symbols represents another type of antifuse called a "pass antifuse". Pass antifuse 15, for example, can be programmed to form a low impedance connection between horizontally extending routing conductor 16 and collinearly extending horizontal routing conductor 17. To realize a user-specific circuit on integrated circuit 1, selected ones of these cross and pass antifuses are "programmed" to connect selected routing conductors together. Which antifuses are programmed and which antifuses are left unprogrammed determines how the logic elements in the logic modules are interconnected and therefore determines the resulting circuit.
For background information on field programmable gate arrays employing antifuses, the reader is referred to: the 1994 QuickLogic Data Book, 1994, pages 2-10 through 2-15; the 1995 Actel FPGA Data Book and Design Guide, 1995, pages 1-109 through 1-139, 1-160 through 1-202, 1-229 through 1-269, and 3-17 through 3-41. The contents of these documents are incorporated herein by reference.
FIG. 2 (Prior Art) illustrates an interface cell 18 of an integrated circuit employing antifuses. Interface cell 18 is connectable to a switch box 19 through "pass" antifuses 20-23. Interface cell 18 contains a bonding pad 24, an input buffer 25, an output buffer 26, and a two-input OR gate 27.
A shortcoming of this interface cell structure is that if input buffer 25 is to be coupled to a horizontally extending routing conductor other than routing conductor 28, then more than one antifuse will have to be programmed. Assume that routing conductor 28 is a short segmented routing conductor (one type of routing conductor) and that routing conductor 30 is a relatively long unsegmented routing conductor (another type of routing conductor). If it were desired to couple input buffer 25 to the long type of routing conductor to transmit an incoming signal across the integrated circuit efficiently, then more than one antifuse would have to be programmed.
For example, to connect the output lead of input buffer 25 to routing conductor 30 (the desired type of routing conductor in this example), pass antifuse 20, cross antifuse 32, and cross antifuse 33 are programmed. Conductor 34 is therefore connected to horizontal routing conductor 28, which is connected to vertical routing conductor 35, which is in turn connected to horizontal routing conductor 30. As a result, the structure of FIG. 2 requires three antifuses to be programmed in order to supply an incoming signal onto the desired type of horizontally extending routing conductor.
Moreover, horizontally extending routing conductor 28 is coupled to horizontally extending routing conductor 30 even though it is not the desired horizontal routing conductor. Horizontally extending routing resources are therefore also wasted.
An improved interface cell and interconnect structure is therefore desired.